Design issues and experimental characterization of a continuously-tuned adaptive CMOS LNA

This paper presents the design implementation and experimental characterization of an adaptive Low Noise Amplifier (LNA) intended for multi-standard Radio Frequency (RF) wireless transceivers. The circuit —fabricated in a 90-nm CMOS technology— is a two-stage inductively degenerated common-source topology that combines PMOS varactors with programmable load to make the operation of the circuit continuously tunable. Practical design issues are analyzed, considering the effect of circuit parasitics associated to the chip package and integrated inductors, capacitors and varactors. Experimental measurements show a continuous tuning of NF and Sparameters within the 1.75-2.23GHz band, featuring NF19.6dB and IIP3> −9.8dBm, with a power dissipation < 23mW from a 1-V supply voltage.Ministerio de Ciencia e Innovación (FEDER) TEC2007-67247-C02-01/MICJunta de Andalucía, Consejo Regional de Innovación, ciencia y empresa TIC-253

Design of an adaptive LNA for hand-held devices in a 1-V 90-nm standard RF CMOS technology: From circuit analysis to layout

This paper deals the design of a reconfigurable Low-Noise Amplifier (LNA) for the next generation of wireless hand-held devices by using a lumped circuit approach based on physical laws. The purpose is not only to present simulation results showing the fulfillment of different standard specifications, but also to demonstrate that each design step has a physical meaning such that the mathematical design flow is simple as well as suitable for hand-work in both laboratory and classroom. The circuit under analysis, which is designed according to technological design rules of a 90nm CMOS technology, is a two-stage topology including inductive-source degeneration, MOS-varactor based tuning networks, and programmable bias currents. This proposal, with reduced number of inductors and minimum power dissipation, adapts its performance to different standard specifications; the LNA is designed to cope with the requirements of GSM (PCS1900), WCDMA, Bluetooth and WLAN (IEEE 802.11b-g). In order to evaluate the effect of technology parasitics on the LNA performance, simulation results demonstrate that the LNA features NF16dB, S11-3.3 dBm over the 1.85-2.48 GHz band. For all the standards under study the adaptive power consumption varies from 25.3 mW to 53.3mW at a power supply of 1-V. The layout of the reconfigurable LNA occupies an area of 1.8mm2.Este trabajo presenta el diseño de un amplificador de bajo ruido, LNA (del inglés Low‐Noise Amplifier) reconfigurable para la siguiente generación de dispositivos portátiles de comunicación inalámbricos, usando la aproximación de circuitos concentrados sustentada en leyes físicas. El propósito de este trabajo no es sólo presentar resultados de simulación que muestran el cumplimiento de especificaciones para cada estándar, sino también demostrar que cada paso de diseño tiene un significado físico haciendo que el procedimiento matemático de diseño sea simple y adecuado para el trabajo a mano tanto para actividades en laboratorio como en el aula. El circuito bajo análisis, diseñado en una tecnología CMOS 90nm, consta de dos etapas que incluyen degeneración inductiva de fuente, redes de entonado basadas en varactores MOS, y corrientes de polarización programables. Esta propuesta, con reducido número de inductores y mínima disipación de potencia, adapta su desempeño a las diversas especificaciones de cada estándar; el LNA se diseña para cubrir los requerimientos de GSM (PCS1900), WCDMA, Bluetooth y WLAN (IEEE 802.11b‐g). Para evaluar el efecto de las no idealidades de la tecnología en el desempeño del LNA, las simulaciones demuestran que el circuito cumple parámetros como NF16dB, S11‐3.3dBm en la banda 1.85‐ 2.48GHz. Para todos los estándares bajo estudio, el consumo adaptivo de potencia varía de 25.3 mW a 53.3mW usando una fuente de alimentación de 1‐V. El patrón geométrico del LNA reconfigurable consume un área de 1.8mm2

Flexible CMOS low-noise amplifiers for beyond-3G wireless hand-held devices

This paper explores the use of reconfigurable Low-Noise Amplifiers (LNAs) for the implementation of CMOS Radio Frequency (RF) front-ends in the next generation of multi-standard wireless transceivers. Main circuit strategies reported so far for multi-standard LNAs are reviewed and a novel flexible LNA intended for Beyond-3G RF hand-held terminals is presented. The proposed LNA circuit consists of a two-stage topology that combines inductive-source degeneration with PMOS-varactor based tuning network and a programmable load to adapt its performance to different standard specifications without penalizing the circuit noise and with a reduced number of inductors as compared to previous reported reconfigurable LNAs. The circuit has been designed in a 90-nm CMOS technology to cope with the requirements of the GSM, WCDMA, Bluetooth and WLAN (IEEE 802.11b-g) standards. Simulation results, including technology and packaging parasitics, demonstrate correct operation of the circuit for all the standards under study, featuring NF13.3dB and IIP3>10.9dBm, over a 1.85GHz-2.4GHz band, with an adaptive power consumption between 17mW and 22mW from a 1-V supply voltage. Preliminary experimental measurements are included, showing a correct reconfiguration operation within the operation band

Design of a 1-V 90-nm CMOS adaptive LNA for multi-standard wireless receivers

This paper presents the design of a reconfigurable Low-Noise Amplifier (LNA) for the next generation of wireless hand-held devices. The circuit, based on a lumped-approach design and implemented in a 90nm standard RF CMOS technology, consists of a two-stage topology that combines inductive-source degeneration with MOS-varactor based tuning networks and programmable bias currents, in order to adapt its performance to different standard specifications with reduced number of inductors and minimum power dissipation. As an application, the LNA is designed to cope with the requirements of GSM (PCS1900), WCDMA, Bluetooth and WLAN (IEEE 802.11b-g). Simulation results, including technology parasitics, demonstrate correct operation of the LNA for these standards, featuring NF16dB, S11 -3.3 dBm over the 1.85-2.48 GHz band, with an adaptive power consumption between 25.3 mW and 53.3mW. The layout of the LNA occupies an area of 1.18×1.18 μm2. [ES]: En este artículo se presenta el diseño de un LNA (del Inglés Low–Noise Amplifier) configurable para la próxima generación de dispositivos digitales personales. El circuito, diseñado con la aproximación de circuitos concentrados e implementado en una tecnología CMOS, 90nm, de RF, consta de una topología formada por dos etapas que combina degeneración inductiva de fuente, redes de entonado basada en varactores, y circuitos de polarización programables para adaptar el desempeño a las diferentes especificaciones del estándar con reducido número de inductores y mínima disipación de potencia. Como aplicación, el LNA que se diseña satisface los requerimientos de GSM (PCS 1900), WCDMA, Bluetooth y WLAN (IEEE 802.11b–g). Los resultados de simulación, incluyendo el efecto de los elementos parásitos, demuestran una correcta operación del para LNA los estándares mencionados, obteniendo NF–3.3 dBm en la banda 1.85–2.48 GHz band, con un consumo de potencia entre 25.3mW y 53.3mW. El patrón geométrico del LNA ocupa un área de 1.18 x 1.18 µm2.Ministerio de Ciencia y Educación TEC2004-01752/MICMinisterio de Industria,Turismo y Comercio FIT-330100-2006-134 SPIRI